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What will computer chips look like in 2045?
Hraness wrote this summary from a saved copy of the source. Quotations are taken word for word from the source.
gist
Dwarkesh Patel tours Intel's most advanced fab and interviews its technical leaders on future chips and the AI demand shock. Engineers explain how a node like 14A is brought up and why Intel uses High-NA EUV while TSMC does not. They also cover how gate-all-around, backside power, ruthenium wires, CFET and hybrid bonding move from lab to production. CTO Pushkar Ranade says global tool supply could roughly double, not 10x, leading-edge wafer output.
ideas
- Limit innovation per node. Chris Auth says 10nm slipped because Intel attempted aggressive scaling without EUV, so Intel now gates technologies with maturity metrics to stay on schedule.
- Backside power changes the litho math. Moving power lines under the transistors relaxes front-side pitches enough for single-pass High-NA printing at Intel, while TSMC would still need multiple passes.
- New structures take decades. FinFET and gate-all-around were both shown around 1988 to 1989 but reached volume production about a decade apart, and CFET faces deep etch, fill and heat limits.
- Hybrid bonding has a long runway. Intel ships 25 micrometer pitch in Foveros, works below 10 in the lab, and cites published reliability data at 0.45 micron.
- Tools cap the AI buildout. Ranade says ASML makes fewer than 100 EUV tools a year, fabs are about 80% fixed cost, and Intel would have invested more a year ago had it known.
quotes
“Not 10X, but probably 2X, yes.”
“If you want to wait for a complete data set, you’ve waited too long.”
“Had we known what we know today, we would have invested more like a year ago.”